Principal Design Verification Engineer

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ADI - Analog Devices

Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market;
Complete verification ownership – Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure;
Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals;
Actively explore and deploy techniques like Formal verification to achieve faster turnaround time on verification;
Debug efficiently and clearly articulate gating issues to engineering leads;
Integrate the block level testbench at SOC level and verify SOC integration;
Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.

Electronic Engineering/Computer Engineering degree with 10+ years of progressive experience in Verification;
Should have demonstrated experience in developing UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure and assertion development;
Strong understanding and experience of Verilog and System Verilog;
Excellent debug and problem-solving skills;
Has experience with both IP and SOC level verification;
Self-motivated, diligent and has an eye for detail;
Knowledge in AHB/AXI/APB/SPMI protocols is desirable; Experience in Power aware simulations or Formal Verification is a big plus;
Experience in Verilog-AMS, analog behavior modelling is desirable;
Understanding of Buck-Boost/Inverse Buck-Boost, LDOs, BG reference concepts in the form of projects or coursework is a plus;
Proficiency in Scripting languages and utilities including Makefile, Python, Perl etc.;
Good written and verbal communication skills.