Digital Design and Verification Engineer

onsemi

Mechelen, Belgium

Position description

Join the onsemi mixed-signal design and product team and help us to exceed the expectations of our customers. Your career will be paved with interesting and varied challenges in the fascinating world of microelectronics, with a strong focus on quality. The projects run in the design center are projects for automotive, industrial and medical applications, in close collaboration with leading customers in the market, using high voltage low power mixed-signal technologies.

We are looking to expand our design team with a Digital IC Design and Verification Engineer. You will participate to the development of IPs and of test environments for our leading edge ICs.

As digital design and verification engineer you will be part of a multi-functional product development team under the lead of a project leader and will be responsible for the digital verification of mixed signal SoC (System on Chip). You are involved in the translation of customer requirements into HW representation using onsemi processes and IP’s, the verification of the digital part of mixed-signal SoC and the support of the products during prototype evaluation, qualification and start-up of volume production. You will work with modern methodologies using EDA tools from established tool vendors (Cadence, Mentor, Synopsys).

You will also be responsible for driving continuous improvement and adoption of best practices by providing expert reviews, facilitating root cause analysis and corrective action plans, training engineers on approved design engineering processes, and maintaining analog/mixed-signal process and checklist documents.

Responsibilities

Digital architecture definition according to requirements;
Digital Design Plan development, estimation and scheduling;
Interaction with IP department;
Digital Modules RTL coding in synthesizable System-Verilog;
Integration of modules in a top-level module;
Full digital design verification cycle starting from specification;
Digital Verification Plan development, estimation and scheduling;
Digital Verification top-level test definition and implementation;
UVM and SystemVerilog-based Digital Verification environment definition and development;
Writing verification plans based on requirements, building testbenches, writing IP and system level testcases, following up the verification team, issue reporting and tracking;
Back-end activities (synthesis, ATPG, sign-off).

Qualifications

MS degree in Electrical Engineering or Computer Science with experience in HDL languages (Verilog, SystemVerilog);
5+ years of experience in digital design and/or verification with hands on experience with SystemVerilog, Verilog and UVM;
Experience in SoC design flow – RTL design, simulation, verification, DFT, signoff (Cadence, Synopsys and Mentor EDA tools);
Strong experience with verification techniques like constrained random generation, functional coverage, cover points, assertions etc.;
Experience with regression testing and verification management (Jenkins/Cadence vManager/Questa VRM);
Scripting programming skills: TCL, PERL, Linux shell scripting, etc.;
Understanding of CMOS technology;
Interest in FPGA and PCB design (used for proof of concept activities);
Experience in MCU programming and DSP is a plus;
Team player that is able to work independently and to interface effectively with team members and customers across many locations worldwide (fluency in English is a must);
Willing and able to learn new subjects, find solution for challenging issues, creative.