Staff Design Verification Engineer

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ADI - Analog Devices

Verification of complex designs and sub-systems using leading edge verification methodologies
Contribute and influence the decisions on methodologies/strategies to be adopted for the verification. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
Architect the test bench and develop in UVM or Formal based verification approaches.
Proficient in developing unit and SoC level test benches using UVM. Integrate the block test bench in chip-level UVM environment and verify integration.
Define test-plans, tests, and verification methodology for block/chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
Continuous interaction with analog co-sim and firmware team.
Managing scripts written in TCL/Perl/Python for different verification aspects.
Coding up in C tests on M3 Series Cortex based products.
Topics of interest: processor architectures, DSP, power sequences, DC-DC converters, low power design, memory interfaces...
Technically mentor and guide junior verification engineers on SoC Verification.
Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team.

Bachelor’s or master’s degree, in Engineering (Electronic Engineering) or equivalent.
Excellent debugging and analytical skills.
10-15 years in ASIC design verification.
Experience with HW emulation or FPGA prototyping.
Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing.

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