Verification Engineer

Capgemini

Stockholm, Sweden

We're seeking an experienced Verification Engineer to drive innovation in the rapidly advancing field of telecommunications. As part of the ASIC IP team, you'll play a key role in shaping the future of 5G and 6G technology. Your expertise and insights will be essential in delivering top-quality IPs that push the boundaries of global connectivity. You’ll turn transformative ideas into tangible solutions, all within a collaborative, creative culture that’s dedicated to making a meaningful impact on the world of connectivity.

Responsibilities of the Candidate

Design and implement a thorough verification plan, including detailed specifications.
Architect and enhance state-of-the-art verification environments.
Build and maintain UVCs to ensure thorough design verification.
Establish testbench infrastructure and create test cases and sequences using UVM-SV (System Verilog).
Apply both random and directed testing methods to identify hidden bugs.
Utilize advanced coverage techniques to achieve comprehensive verification.
Execute and manage functional verification using coverage-driven methodologies.
Make key architectural decisions for the testbench based on specific design features.
Advocate for ongoing improvements in product quality, efficiency, and workflow processes.
Strong debugging skill for TB, RTL and verification environment.

Qualification and Skills

Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels using System Verilog UVM, with potentially 15 years of Verification experience.
Hands-on experience in designing UVM test environments and achieving coverage closure.
Proficiency in verification planning, testbench development, test case creation, functional coverage, and code coverage analysis.
An insatiable curiosity, eager to learn something new daily and apply new knowledge for meaningful impact.
Strong problem-solving skills: you approach challenges as opportunities for innovation.
A collaborative mindset and the ability to work independently, paired with outstanding communication skills.
A results-driven approach with a commitment to continuous improvement, constantly seeking faster and more innovative solutions.
A master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Nice to have skills

Experience in Perl, TCL.
Knowledge of Formal Verification and Validation.
Experience working on different levels of ASIC Verification (IP/Subsystem/SOC Design).

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